Many types of memory devices such as Dynamic Random Access Memory (“DRAM”) or Static Random Access Memory (“SRAM”) devices store information in memory cells arranged as an array of selectable rows and columns. Lines connecting each row are commonly referred to as word lines (“WL”). Each column typically comprises a bit line and its complement. Word lines are activated to select the desired memory cell for memory operations. Data stored by each memory cell is transferred to a sense amplifier (“SA”) circuitry via the bit lines for amplification.
A sense amplifier is driven by an enable signal that is generated from a sense amplifier enable (“SAE”) signal generator. The SAE signal generator typically receives an external clock signal applied from an external source and generates a SAE signal.
To perform a sensing operation after an address is applied from an external source, data stored in a memory cell (a bit cell) drives a pair of bit lines up to a predetermined level. The SAE signal is activated. The SAE signal generator typically is configured so as to receive the external clock signal and then activate the SAE signal after a delay of a predetermined period of time instead of a programmable delay.
A conventional self-timed approach for SAE signal generator generates a SAE signal from the rising edge of a clock signal. The pulse width of both WL and SAE are determined by internal self-resetting path, which is highly sensitive to processing, voltage, and temperature (“PVT”) variations. Furthermore, inaccurate models can cause frequency independent failures.
Another conventional clock based approach generates the signal WL during the entire clock high phase. At the clock signal falling edge, the SAE signal is generated by the SAE signal generator. Since during this clock cycle, the WL and SAE are both active, the bit lines will need to be pre-charged at an additional clock cycle, thus using another clock cycle for each read operation, resulting in low throughput. At the same time, the WL pulse may be too long at lower clock frequency, and this wastes power.
Therefore, a solution is needed to generate SAE signals to eliminate the additional clock cycle used in the conventional clock based approach, to increase the throughput. A solution is also needed to eliminate the internal self-resetting path in the conventional self-timed approach so that the resulting SAE signal can be more tolerant to PVT variations, which has become increasingly difficult with increased PVT variations in advanced semiconductor processes.